EPCS1SI8N

SOIC, FPGA, 2.7V to 3.6V

Rated 5 Rating 5 | reviews | Write a review

Price:: US $0.50~0.60 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
	US $0.50~0.60

PartNumber:: EPCS1SI8N

Brand:: Altera Corporation - ALTR | Pack: DIP | D/C: 07+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

Place Order via Escrow Service

Sold By

Ms. Lisa's store

(China (Mainland))

add to my favourite

100% Positive feedback

Detailed seller ratings

Visit Store

Contact Now

Esrcow Service

Place orders confidently and securely via it

Safe payments
Quick and easy transactions
Free service charges

Learn More >>

Previous Next

Products Upload time: 2011-07-27

From Other Seller

Part Number:EPCS1SI8N
US $0.50 - 0.60
TMS320C6414TBGLZA7

US $58.00 - 65.00 / Piece
(0) Remove
LM64P101

US $240.00 - 300.00 / Piece
(0) Remove
Quantity:

piece

Product Summary

The EPCS1SI8N is an FPGA. It controls the nSTATUS and CONF_DONE pins during configuration in AS mode. If the CONF_DONE signal does not go high at the end of configuration or if the signal goes high too early, the EPCS1SI8N will pulse its nSTATUS pin low to start reconfiguration. Upon successful configuration, the EPCS1SI8N releases the CONF_DONE pin, allowing the external 10-k resistor to pull this signal high. Initialization begins after the CONF_DONE goes high. After initialization, the FPGA enters user mode.

Parametrics

EPCS1SI8N absolute maximum ratings: (1)Supply voltage:–0.6V to 4.0V; (2)DC input voltage:–0.6V to 4.0V; (3)DC VCC or GND current:15mA; (4)DC output current per pin:–25mA to 25mA; (5)Power dissipation:54mW; (6)Storage temperature:-65℃ to 150℃; (7)Ambient temperature:–65℃ to 135℃; (8)Junction temperature:135℃.

Features

EPCS1SI8N features: (1)1-, 4-, 16-, 64-, and 128-Mbit flash memory devices that serially configure Arria series, Cyclone series, all device families in the Stratix series except the Stratix device family, and FPGAs using the active serial (AS) configuration scheme; (2)Easy-to-use four-pin interface; (3)Low cost, low-pin count, and non-volatile memory; (4)Low current during configuration and near-zero standby mode current ; (5)2.7-V to 3.6-V operation; (6)Enables the Nios processor to access unused flash memory through AS memory interface; (7)Re-programmable memory with more than 100,000 erase/program cycles; (8)Write protection support for memory sectors using status register bits; (9)In-system programming support with SRunner software driver; (10)In-system programming support with USB Blaster, EthernetBlaster, or ByteBlaster II download cables; (11)Additional programming support with the Altera Programming Unit (APU) and programming hardware from BP Microsystems, System General, and other vendors; (12)Delivered with the memory array erased (all the bits set to 1).